Contribution (Oral) The interplay of self-heating and unintentional dopants on the operation of nanowire transistors

The ultimate goal in transistor scaling is to successfully fabricate (with acceptable yield) structures with ever smaller dimensions to be able to put more functions on a chip. At the end of the roadmap (more than Moore scenario), amongst other devices, nanowire transistors are speculated to replace conventional MOSFET devices. In fact, the 22 nm technology node is based on FinFET technology. Since nanowire transistors belong to the category of silicon on insulator devices, it is expected that self-heating effects will have impact on the transistor operation and will degrade the ONcurrent. In our previous studies [1] we have shown that the degradation effect decreases with shrinking device dimensions due to the pronounced non-stationary transport that manifests itself via the pronounced velocity overshoot effect. Another important aspect related to operation of nanowire transistors is the amount of current degradation due to presence of charged traps placed at arbitrary location of the channel whose charge state can be positive or negative.